NEXTGenIO @ ISC-HPC 2016

The annual ISC-HPC conference was again held in Frankfurt last week, from 19-23 June. NEXTGenIO had a very successful conference, holding several talks and presentations across the five days.

These included:

A talk at the Intel Collaboration Hub, given by Michele Weiland of project partner EPCC on Tuesday, 21st June. This talk, entitled "Addressing the I/O bottleneck", outlines the advances the project is working on and how this affects the development of new systems on the path to Exascale.
A BoF session on Wednesday, 22nd June, entitled, "BoF 15: Monitoring Large-Scale HPC Systems: Data Analytics & Insights". This session was moderated by Hans-Christian Hoppe and Marie-Christine Sawley of project partners Intel, and Mark Parsons from project partner EPCC presented the project at this BoF session. The session was designed to "address issues and approaches in large-scale HPC monitoring from the perspectives of system administrators, end users, and vendors".
A second BoF session on Wednesday 22nd June, entitled, "BoF 16: Exascale I/O: Challenges, Innovations & Solutions". This session was moderated by Hans-Christian Hoppe from project partner Intel and Michele Weiland from project partner EPCC. Mark Parsons from EPCC was again an inivited speaker. The session addressed "system architecture and components, the I/O system SW stack and APIs for HPC and HPDA applications. A panel-style discussion with the audience will contribute to a consolidated view of the field and its evolution. The presenters will represent significant I/O development efforts in Europe (DEEP-ER, NEXTGenIO and SAGE projects), and world-wide (Intel, Seagate)."
A workshop on Thursday, 23rd June, entitled, "Form Follows Function – Do Algorithms & Applications Challenge or Drag behind the Hardware Evolution?" This workshop was organised on behalf of the ExaHYPE project. Mark Parsons presented the project. The aim of the workshop was to "sketch answers to a couple of questions from an algorithm/application point of view:
- How do predictions on new hardware features impact the projects' research agenda? Notably, how do the hardware roadmaps shape algorithm development today?
- What characteristics make some applications exascale candidates? Do these characteristics stem from particular algorithmic ideas, and are there constraints on the type of algorithms and applications that we will see soon on the exascale level?
- Do statements on hardware-aware algorithm development and hardware-software co-design affect particular machine aspects, or is notably the last term a buzzword?
- To which degree can simulation codes have an impact on what machines are designed?"