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Hardware Architecture - NEXTGenIO Architecture White Paper

Adrian Jackson, Iakovos Panourgias (EPCC), Bernhard Homölle (SVA), Alberto Miranda, Ramon Nou, Javier Conejero (BSC), Marcelo Cintra (Intel), Simon Smart, Antonino Bonanni (ECMWF), Holger Brunst, Christian Herold, Sarim Zafar (TU Dresden)

NEXTGenIO is developing a prototype high-performance computing (HPC) and high-performance data analytics (HPDA) system that integrates byte-addressable storage class memory (SCM) into a standard compute cluster to provide greatly increased I/O performance for computational simulation and data analytics tasks.

To enable us to develop a prototype that can be used by a wide range of computational simulation application, and data analytic tasks, we have undertaken a requirements-driven design process to create hardware and software architectures for the system. These architectures both outline the components and integration of the prototype system, and define our vision of what is required to integrate and exploit SCM to enable a generation of Exascale systems with sufficient I/O performance to ensure a wide range of workloads can be supported.

The hardware architecture, which is the focus of this White Paper, is designed to scale up to an ExaFLOP system. It uses high-performance processors coupled with SCM in NVRAM (non-volatile random access memory) form, traditional DRAM memory, and an Omni-Path high-performance network, to provide a set of complete compute nodes that can undertake both HPC and HPDA workloads.

Supporting Documents: 
NEXTGenIO_whitepaper2_OCT18_LO.pdf 866.7 Kb [5 download(s)]